Logic for calculating bit error rate in a data communication sys

Details Logic for calculating bit error rate in a data communication sys Logic for calculating bit error rate in a data communication sys

1984-07-19

1986-10-07

Atkinson, Charles E.

Excavating

G06F 1100

Patent

active

046163620

ABSTRACT:
A system for determining the bit error rate in a communication system comprising logic for generating a stream of data bits, bit extracting logic for periodically extracting N consecutive bits after the occurrence of every Mth bit, where the N consecutive bits are divided into a group of A bits and a group of C bits, where A and C are equal integers, and a single B bit is positioned between the group of A and C bits, where M>>A, where the N bits can be any combination of binary 1's and 0's. Logic extracts and stores a finely quantized sample of the B bit of each group of N bits. An adder adds an auxiliary group of X bits to the N bits to form a memory address consisting of A, B, C, and X bits. A plurality of memories each has storage locations for a single finely quantized B bit sample. Each memory further is selectable by a unique combination of the binary bits A+B+C with any given storage location in each memory being accessible by various combinations of the X bits. Appropriate logic by a predetermined algorithm calculates the current probability of bit rate error.

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patent: 4034340 (1977-07-01), Sant'Agostino
patent: 4054863 (1977-10-01), Goodman et al.
patent: 4234954 (1980-11-01), Lange et al.
patent: 4367550 (1983-01-01), Douverne
patent: 4375099 (1983-02-01), Waters et al.
patent: 4387461 (1983-06-01), Evans

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