Semiconductor memory having stacked capacitor

Details Semiconductor memory having stacked capacitor Semiconductor memory having stacked capacitor

1990-08-13

1991-04-30

James, Andrew J.

357 41, 357 49, 357 51, 357 54, 357 59, 357 71, H01L 2968, H01L 2702, H01L 2348

Patent

active

050123106

ABSTRACT:
A megabit dynamic random access memory realizing high integration and high reliability is disclosed. The need for an allowance for photomask alignment which is carried out to produce a stacked capacitor memory cell is eliminated. The plate electrode of each memory cell is isolated from the corresponding data line in a memory array by means of an insulating film which is self-alignedly provided around the plate electrode.

REFERENCES:
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patent: 4742018 (1988-05-01), Kimura et al.
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patent: 4760034 (1988-07-01), Barden
patent: 4855801 (1989-08-01), Kuesters
Ohta, K. et al., "Quadruply Self Aligned . . . ", IEEE Trans., Electron Dev., vol. ED-29, No. 3, Mar. 1982, pp. 368-376.
L. Glasser, D. Dobberpuhl, "The Design & Analysis of VLSI Circuits", 1985, p. 398.

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