Timing loop method and apparatus for PRML data detection

Details Timing loop method and apparatus for PRML data detection Timing loop method and apparatus for PRML data detection

1992-06-15

1995-05-16

Chin, Stephen

Pulse or digital communications

Synchronizers

375290, 375293, 360 32, H04L 700, G11B 509

Patent

active

054168066

ABSTRACT:
Timing loop apparatus and method are provided for data detection in a partial-response maximum-likelihood (PRML) data channel. The PRML data channel includes an analog to digital converter (ADC) providing samples to a digital filter during a tracking mode and to a gain and timing control during an acquisition mode. Sample values from the ADC are received at peaks and zeros on sync field pattern. An error absolute value is calculated from the received ADC sample values and an error sign of the calculated error absolute valve calculated using a most significant bit of the current and a previous sample. Timing correction values are calculated responsive to the calculated error absolute value and applied to a clock gated register that latches and holds the generated timing correction values for a predefined number of clock cycles.

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