Signal delay device using CMOS supply voltage control

Details Signal delay device using CMOS supply voltage control Signal delay device using CMOS supply voltage control

1988-12-21

1991-04-30

Hudspeth, David

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307451, 307585, 307592, H03R 512

Patent

active

050121413

ABSTRACT:
A signal delay device comprises a CMOS gate circuit having an input terminal to which a binary input signal to be delayed is applied, an output terminal from which a delayed signal is derived and power voltage supply terminals to which operation power voltages are applied. The delay time of the CMOS gate circuit depends upon voltage applied to it and, utilizing this phenomenon, voltage control means is provided in a power supplying path for the CMOS gate circuit for controlling voltage applied to the CMOS gate circuit, The signal delay device using the CMOS gate circuit is applied to various circuits including an analog signal delay circuit, a jitter absorption circuit and a fixed head type magnetic tape reproducing device.

REFERENCES:
patent: 3914702 (1975-10-01), Gehweiler
patent: 3996481 (1976-12-01), Chu et al.
patent: 4473762 (1984-09-01), Iwahashi et al.
patent: 4482826 (1984-11-01), Ems et al.
patent: 4514647 (1985-04-01), Shoji
patent: 4585955 (1986-04-01), Uchida
patent: 4638184 (1987-01-01), Kimura

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