Semiconductor memory device having peripheral circuit and interf

Details Semiconductor memory device having peripheral circuit and interf Semiconductor memory device having peripheral circuit and interf

1996-02-05

1998-04-14

Le, Vu A.

Static information storage and retrieval

Format or disposition of elements

365 63, 257350, 257351, 257353, 257354, G11C 1124

Patent

active

057400997

ABSTRACT:
A semiconductor dynamic random access memory device has a memory cell array fabricated on a silicon-on-insulator region and peripheral and interface circuits fabricated on a bulk region; even if the circuit components of the peripheral circuit are increased together with the memory cells, the bulk region effectively radiates the heat generated by the peripheral and interface circuits, thereby preventing the memory cells from a temperature rise.

REFERENCES:
patent: 5371401 (1994-12-01), Kozaburo
patent: 5495437 (1996-02-01), Morihara
"An SOI-DRAM with Wide Operating Voltage Range by CMOS/SIMOX Technology" by 1994 IEEE International Solid-State Circuits Conference pp. 138-139, 324 vol. 37.
Patent Abstracts of Japan, vol. 017, No. 264 (E-1370), 24 May 1993 Takeshi JP 5006979.

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