Content-addressable-memory control circuit

Details Content-addressable-memory control circuit Content-addressable-memory control circuit

1995-11-28

1998-04-14

Nelms, David C.

Static information storage and retrieval

Associative memories

Ferroelectric cell

36518907, G11C 1500

Patent

active

057400970

ABSTRACT:
A timing control signal SR is made low to switch on a P-MOSFET and switch off an N-MOSFET, and with an N-MOSFET as a boundary, a voltage V.sub.MATCHI on the side of a NOT circuit of a match-line is pulled up to a power supply voltage V.sub.DD. During this, a comparison operation is done in a content addressable memory cell, and an N-MOSFET is switched on or off according to the result of comparison. Next, the control signal SR goes to a logic high level, so the P-MOSFET is switched off and the N-MOSFET is switched on. As a result, if the N-MOSFET is on, the voltages V.sub.MATCHI and V.sub.MATCH will be reduced to a ground level, but the through current is prevented because the P-MOSFET is off. If the N-MOSFET is off, the V.sub.MATCH will be pulled up to V.sub.DD -V.sub.tn (V.sub.tn is the threshold voltage of the N-MOSFET), the V.sub.MATCHI will be held to V.sub.DD by the NOT circuit and the P-MOSFET, and a signal representative of a result of comparison will be output from the NOT circuit. Also, by the interval of the N-MOSFET, the parasitic capacitance of the portion on the side of the content addressable memory cell of the match-line with the MOSFET as a boundary disappears from the portion on the side of the pull-up means from the portion on the side of the NOT circuit with the voltage drop element as a boundary, so the pull-up of the portion on the side of the NOT circuit with the MOSFET as a boundary becomes fast.

REFERENCES:
patent: 5396449 (1995-03-01), Atallah et al.
patent: 5483480 (1996-01-01), Yoneda

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