Self-timed multiplier array

Details Self-timed multiplier array Self-timed multiplier array

1995-08-21

1998-04-14

Mai, Tan V.

Boots, shoes, and leggings

G06F 752

Patent

active

057400946

ABSTRACT:
Logic circuitry implemented in a pipeline manner receives a request signal along with received data into the pipeline and proceeds to insure that each successive stage within the pipeline is placed into a standby state and out of a precharge state previous to the arrival of the data wave into each of the successive stages. The circuitry also resets each of the stages after a stage has evaluated the data. The logic circuitry may be employed within a multiplier array in a processor.

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patent: 5093809 (1992-03-01), Schmitt-Landsiedel
patent: 5150325 (1992-09-01), Yanagisawa et al.
patent: 5204841 (1993-04-01), Chappell et al.
patent: 5289403 (1994-02-01), Yetter
patent: 5345472 (1994-09-01), Podkowa

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