Method of improvement ESD for LDD process

Details Method of improvement ESD for LDD process Method of improvement ESD for LDD process

1993-10-04

1995-05-16

Chaudhuri, Olik

Fishing, trapping, and vermin destroying

437 44, 437 54, H01L 2170, H01L 2700

Patent

active

054160367

ABSTRACT:
A method of forming an ESD protection device simultaneously with an integrated circuit which includes FET devices is described. A silicon substrate on which there are field oxide regions, gates, and active regions is provided. A first ion implant in a vertical direction is performed of a conductivity-imparting dopant, into the active regions of the ESD protection device and the FET devices. An insulating layer is formed over the ESD protection device and the FET devices, and over the field oxide regions. The insulating layer is patterned to create spacers adjacent to the gates of both the ESD protection device and the FET devices. The spacers are removed from the gate of the ESD protection device. A second ion implant in a vertical direction is performed of a conductivity-imparting dopant with higher concentration than dopant from the first ion implant, into active regions of both the ESD protection device and the FET devices.

REFERENCES:
patent: 4753898 (1988-06-01), Parrillo
patent: 5087582 (1992-02-01), Campbell et al.
patent: 5142345 (1992-08-01), Miyata
patent: 5246872 (1993-09-01), Mortensen

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