Single line propagation adder and method for binary addition

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G06F 750

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041527755

ABSTRACT:
A propagation line adder may be fabricated by replicating a unit circuit along a single sense propagation path. Each unit circuit corresponds to a bit of the same order of magnitude of the binary addends. Selected segments of the sense propagation path are set at a specified logical potential value and are coupled according to control signals generated within the unit circuit in response to the addend bits. A sense amplifier, coupled to each segment of the sense propagation paths, detects the state on corresponding segments of the sense propagation path. The propogation line adder implements an algorithm which produces the binary sum of two numbers by complementing the exclusive-or function of the addends according to a shifted product function. The shifted product function includes a carry-in bit as its lowest order bit.

REFERENCES:
patent: 3717755 (1973-02-01), Briley
patent: 3743824 (1973-07-01), Smith
patent: 3757308 (1973-09-01), Fosdick
patent: 3843876 (1974-10-01), Fette et al.
patent: 3970833 (1976-07-01), Gehweiler
patent: 4031379 (1977-06-01), Schwartz

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