Method and apparatus for interconnect testing without speed degr

Details Method and apparatus for interconnect testing without speed degr Method and apparatus for interconnect testing without speed degr

1993-12-07

1996-04-30

Voeltz, Emanuel T.

Excavating

371 221, H04B 1700

Patent

active

055131867

ABSTRACT:
A method and apparatus is disclosed for advantageously implementing a full boundary scan test of input and bi-directional paths of an integrated circuit. The present invention provides a full boundary scan test capability with practically no degradation of speed of operation during normal operation of the integrated circuit. Within the integrated circuit under test, boundary scan registers are coupled to each input and bi-directional pin. When placed in a test mode, the corresponding output drivers are tristated for every bi-directional pin of the integrated circuit under test. Then the values of a test signal vector asserted on the pins of the integrated circuit are captured by the boundary scan registers. These captured values are retrieved and output from the integrated circuit so that they can be compared to the asserted test signal vector. Because the integrated circuit does not have any non-test specific output pins, there is no need to override values output from the integrated circuit during a full boundary scan test. Furthermore, because the boundary scan registers capture the test signal vector values but cannot override values, the prior art need to provide a multiplexer in the path of each pin in order to make a full boundary scan test is eliminated. Therefore, the present invention permits a full boundary scan test without placing an overhead penalty on each path to and from the pins of the chip.

REFERENCES:
patent: 5202625 (1993-04-01), Farwell
patent: 5220281 (1993-06-01), Matsuki
patent: 5260948 (1993-11-01), Simpson et al.
patent: 5347520 (1994-09-01), Simpson et al.

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