Fishing – trapping – and vermin destroying
Patent
1996-10-09
1998-04-14
Niebling, John
Fishing, trapping, and vermin destroying
437 41, 437 6, H01L 21265, H01L 4900
Patent
active
057390444
ABSTRACT:
After selectively forming P.sub.+ -type gate regions 14 in the upper surface of a first N.sup.- -type semiconductor substrate 10, gate electrodes 30 are selectively formed on the P.sup.+ -type gate regions. A P.sup.+ -type layer 12 is formed in the lower surface of the N.sup.- -type substrate 10. Recessed portions 26 which can house the gate electrodes are formed in the lower surface of the second N.sup.- -type semiconductor substrate 20 and an N.sup.+ -type layer 22 is formed in the upper surface thereof. After removing impurities from the surfaces of the first and second semiconductor substrates 10 and 20 by RCA cleaning, the surfaces are cleaned with a pure water and are dried by a spinner. Then the substrates 10 and 20 are joined to each other by heating the substrates 10 and 20 at 700.degree.-1100.degree. C. in an H.sub.2 atmosphere, while the upper surface of the first semiconductor substrate 10 is brought into contact with projected portions 29 on the lower surface of the second semiconductor substrate 20. Thus there can be obtained a static induction thyristor, static induction transistor or gate turn-off thyristor, in each of which gate regions and gate electrodes are buried within a semiconductor substrate.
REFERENCES:
patent: 4534033 (1985-08-01), Nishizawa et al.
patent: 4611235 (1986-09-01), Bhagat
patent: 4829348 (1989-05-01), Broich et al.
patent: 4984049 (1991-01-01), Nishizawa et al.
patent: 5086330 (1992-02-01), Minato
patent: 5352909 (1994-10-01), Hori
patent: 5428229 (1995-06-01), Niwayama et al.
patent: 5545905 (1996-08-01), Muraoka t al.
patent: 5648665 (1997-07-01), Terasawa
H. Mitlehner et al., A Novel 8kV Light-Trigger Thyristor with Over Voltage Self Protection, Proc. ISPSD, pp. 289-294 (1990). Month Unknown.
Patent Abstracts Of Japan, vol. 11, No. 7 (E-469 ) Jan. 9, 1987 & JP-A-61 182259 (Toshiba Corp) Aug. 14, 1986, Abstract.
Nikkei Electronics, vol. 1971.9.27 pp. 50-61 (1971). Month Unknown.
J. Nishizawa et al., IEEE Trans on Electron Devices, vol. ED-22(4), pp. 185-197 (1975). Month Unknown.
J. Nishizawa et al., Rev. de Physiquee Applique, T13, pp. 725-728 (1978). Month Unknown.
J. Nishizawa et al., Technical Digest 1980 IEDM pp. 658-661 (1980). Month Unknown.
J. Nishizawa et al., Analysis of Characteristics of Static Induction Thyristor, Vols. ED81-7 & ED84-84, (1981). Month Unknown.
M. Ishidoh et al., Advanced High Frequency GTO, Proc. ISPSD, pp. 189-194 (1988). Month Unknown.
B.J. Baliga et al., The Evolution of Power Device Technology, IEEE Trans on Electron Devices, vol. ED-31, pp. 1570-1591, (1984). Month Unknown.
M. Amato et al., Comparison of Lateral and Vertical DMOS Specific On-Resistance, IEDM Tech. Dig. pp. 736-739, (1985). Month Unknown.
B.J. Baliga, Modern Power Devices, John Wiley Sons, pp. 350-353, (1987). Month Unknown.
Lebentritt Michael S.
NGK Insulators Ltd.
Niebling John
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