Low cost testing method for register transfer level circuits

Details Low cost testing method for register transfer level circuits Low cost testing method for register transfer level circuits

1996-10-31

1998-05-05

Beausoliel, Jr., Robert W.

Excavating

364488, G01R 3128

Patent

active

057486476

ABSTRACT:
An alternative method for testing circuits (H-SCAN) which retains the main advantage of full scan testing, namely, the ability to use combinational automatic test pattern generation (ATPG), while eliminating the high area overhead the long test application time associated with full, scan test methods. The method provides a practical test methodology that can be easily applied to any RT-level specification. The method uses existing connections of registers and other structures available in a high-level specification of a circuit without necessitating the use of scan flip-flops. Test application time is reduced by using the parallelism inherent in the circuit design to load multiple flip-flops in a single clock cycle, without having to add parallel scan chains as done in traditional parallel scan approaches.

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