Method of making JFET structures for semiconductor devices with

Details Method of making JFET structures for semiconductor devices with Method of making JFET structures for semiconductor devices with

1995-10-16

1997-07-29

Nguyen, Tuan H.

Fishing, trapping, and vermin destroying

437 31, 437 54, 437 76, 437 59, 148DIG88, H01L 21265

Patent

active

056521537

ABSTRACT:
A semiconductor device may include complementary NPN and PNP transistors and a JFET that is formed in the same steps as used to form the transistors. The bottom gate of the JFET and the back collector layer of the PNP transistor are doped and up-diffused in the same steps to cause the channel of the JFET and distance between the base and back collector layer of the PNP transistor to be the same. The JFET may have a low voltage capability (less than 5 volt pinch-off voltage) and the PNP transistor may have a breakdown voltage of at least 30 volts.

REFERENCES:
patent: 4403395 (1983-09-01), Curran
patent: 4553318 (1985-11-01), Chandrasekhar
patent: 4729008 (1988-03-01), Bearom
patent: 4939099 (1990-07-01), Seacrist et al.
patent: 5151765 (1992-09-01), Yamauchi
patent: 5296409 (1994-03-01), Merrill et al.

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