Multiplication circuit capable of operating at a high speed with

Details Multiplication circuit capable of operating at a high speed with Multiplication circuit capable of operating at a high speed with

1988-02-16

1989-10-31

Malzahn, David H.

Boots, shoes, and leggings

G06F 750

Patent

active

048781916

ABSTRACT:
A multiplication circuit comprises a zero detector coupled to a multiplier register so as to generate a signal indicative of completion of the multiplication operation when all of predetermined bits of the multiplier register are zero. A right shifter is coupled to the multiplier register so as to shift the input data one bit rightwardly and to put "0" at its most significant bit. The right shifter rewrites the multiplier register with the shifted data having the MSB of "0". Further, a left shifter is coupled to a multiplicand register so as to shift the input data one bit leftwardly and to put "0" at its least significant bit. The left shifter rewrites the multiplicand register with the leftwardly shifted data having the LSB of "0". An adder is coupled to receive a content of a product register and a content of the multiplicand register and to rewrite the product register with the result of an addition between the content of the product register and the content of the multiplicand register when the LSB of the multiplier register is "1".

REFERENCES:
patent: 3761699 (1973-09-01), Sather
patent: 4228518 (1980-10-01), Chamberlin
patent: 4685077 (1987-08-01), Loo
patent: 4745569 (1988-05-01), Yamaoka et al.
Waser, "High-Speed Monolithic Multipliers for Real-Time Digital Signal Processing", Computer, Oct. 1978, pp. 19-28.
Gerberich et al, "Multiplier/Divider Hardware Design Accelerates Microprocessor Throughput", Computer Design, Jun. 1979, pp. 105-112.

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