Test auxiliary circuit for testing semiconductor device

Details Test auxiliary circuit for testing semiconductor device Test auxiliary circuit for testing semiconductor device

1988-06-10

1990-05-15

Smith, Jerry

Excavating

371 212, G01R 3128

Patent

active

049264249

ABSTRACT:
A scan-path comprises a plurality of scan registers connected in series. Expected value data are inputted to the plurality of scan registers by a serial shift operation. Data read out from a RAM which is a circuit under test are applied to parallel input terminals of the scan registers, respectively. If the data applied to the parallel input terminals are different from the expected value data, the data held in the scan registers are inverted. After data of all addresses in the RAM are read out, the data held in the scan registers are read out by the serial shift operation. If any of the data as read out is inverted, it is determined that the RAM is defective.

REFERENCES:
patent: 4601034 (1986-07-01), Sridhar
patent: 4698830 (1987-10-01), Barzilai
patent: 4761768 (1988-08-01), Turner
1985 Internation Test Conference: "A New Parallel Test Approach for Large Memories" by a R. Sridhar, paper No. 13.5, 1985, pp. 462-470.

Affiliated with

Also associated with

Rating

Test auxiliary circuit for testing semiconductor device does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Test auxiliary circuit for testing semiconductor device, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Test auxiliary circuit for testing semiconductor device will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-627653