Boots – shoes – and leggings
Patent
1987-05-11
1990-05-15
James, Andrew J.
Boots, shoes, and leggings
G06F 1306, G06F 1214, G06F 900
Patent
active
049263145
ABSTRACT:
The present invention provides an apparatus and method for use in a computer system, and particularly, a computer system employing memory devices having discrete capacity (i.e., 256K bit, 1M bit, etc.), such as random access memory (RAM). The present invention includes a central processing unit (CPU) coupled through a multiplexor to a plurality of contiguous banks of memory devices. In a typical embodiment, a user inserts a desired number of RAM memory devices having a particular memory capacity into the memory banks. A maximum memory address is defined for each bank as the address which would exist if the highest capacity memory devices available were utilized (e.g., 16M bit/device). On power-up, the CPU sequentially attempts to store the numerical address value of each possible memory address at that address location, from the highest possible contiguous address to the lowest, for the first memory bank. In the event that the CPU attempts to write to a non-existent address, the value is automatically stored at the highest read address in the system. The CPU then sequentially reads each possible memory address from the lowest to the highest. For each address read, the CPU compares the stored value with the address. The fact that the stored value equals the address indicates that the address exists. In the event the stored value does not equal the address, but rather equals the previously read address, the address does not exist and the highest available memory is set to the previous address value. The CPU repeats this procedure for the next bank of memory until the total available memory of the system is determined. A bit value is assigned which corresponds to the available memory size of the first memory bank. This bit value is stored in a register coupled to control logic which controls the operation of the multiplexor and generates row address (RAS) and column address (CAS) signals to access the memory. Memory banks are selected by the control logic based upon the logical state of predetermined address bits outputted by the CPU which are identified by the bit value.
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Apple Computer Inc.
James Andrew J.
Nguyen Viet Q.
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