1990-03-12
1991-07-09
Hille, Rolf
357 231, 357 239.23.4, 357 2312, H01L 2978
Patent
active
050310089
ABSTRACT:
A MOSFET transistor, in which source and drain regions are formed at a certain distance away from each other in a surface area of a semiconductor substrate having a first conductivity type, and a gate electrode is formed on the surface of the substrate through a gate insulating film formed thereon between the source and drain regions, and in which a channel region located in the surface area of the substrate between the source and drain regions is composed of different concentration regions, and a threshold voltage of a high concentration channel region is lower than that of a low concentration channel region.
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patent: 4924277 (1990-05-01), Yamane et al.
patent: 4925807 (1990-05-01), Yoshikawa
IBM Technical Disclosure Bulletin, vol. 22, No. 6, Nov. 1979, "Double Polysilicon Depletion-Mode MOS Transistor Structure", by Varshney, pp. 2292-2293.
S. Ogura et al., "A Half Micron Mosfet Using Double Implanted LDD", IBM., IEDM 82, Tech Digest, 1982, pp. 718-721.
IBM Technical Disclosure Bulletin, vol. 22, No. 6, Nov. 1979, pp. 2292-2293, R. C. Varshney: "Double Polysilicon Depletion-Mode Transistor Structure".
Patent Abstracts of Japan, vol. 9, No. 169 (E-328)[1892], Jul. 13, 1985, JP-60-43863.
Patent Abstracts of Japan, vol. 10, No. 213 (E-422)[2269], Jul. 25, 1986, JP-61-53773.
Hille Rolf
Kabushiki Kaisha Toshiba
Loke Steven
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