Multiplexed PSK demodulator

Details Multiplexed PSK demodulator Multiplexed PSK demodulator

1985-08-05

1987-06-02

Griffin, Robert L.

Pulse or digital communications

Repeaters

Testing

329112, 370 12, H03D 322, H04L 2722

Patent

active

046708871

ABSTRACT:
An improved quadrature differential phase shift keyed signal demodulator for use in a modem is shown. A delay circuit (12) delays an input signal for a portion of a baud time. Synchronous detectors (21, 23) mix the original and delayed input signals with coherent reference signals to obtain detected outputs which are alternately provided to a processor (60) by a multiplexer (25). The processor (60) determines the phase shift and provides the demodulated data. An offset baud clock phase locked loop (40) provides a baud clock which is offset by a ninety degree phase lag. The offset baud clock caused the multiplexer (25) to provide detected outputs to the processor (60) for the center one-half of each baud. The result is a demodulator with fewer components and an improved data error rate.

REFERENCES:
patent: 3944939 (1976-03-01), Le Mouel
patent: 3991377 (1976-11-01), Salazar et al.
patent: 3993956 (1976-11-01), Gilmore et al.
patent: 4019149 (1977-04-01), Kustka et al.
patent: 4064361 (1977-12-01), Kustka et al.
patent: 4253067 (1981-02-01), Caples et al.
patent: 4466108 (1984-08-01), Rhodes
patent: 4481640 (1984-11-01), Chow et al.

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