Split-polysilicon CMOS DRAM process incorporating selective self

Details Split-polysilicon CMOS DRAM process incorporating selective self Split-polysilicon CMOS DRAM process incorporating selective self

1990-03-22

1991-07-09

Chaudhuri, Olik

Fishing, trapping, and vermin destroying

437 34, 437 44, 437 52, 437 57, 357 236, H01L 21265, H01L 21336, H01L 27092, H01L 27108

Patent

active

050305859

ABSTRACT:
A split-polysilicon CMOS DRAM process incorporating selective, self-aligned silicidation of conductive regions and silicon nitride blanket protection of N-channel regions during the etch steps which create P-channel transistor gate spacers, thus avoiding transistor breakdown voltage problems associated with the double etching of the N-channel regions that was heretofore required for the creation of LDD-type P-channel transistors and self-aligned silicidation of conductive regions utilizing a split-polysilicon CMOS process. A CVD anti-silicidation oxide layer and a protective silicon nitride layer are blanket deposited on top of all circuitry following the patterning of the cell plate. The protective nitride layer protects the N-channel regions during the etches used to create the P-channel channel transistor gate spacers. Following the stripping of the protective nitride layer, an optional antisilicidation thermal oxide layer may be grown on the P-channel substrate. A silicidation isolation mask may be utilized to prevent removal of certain portions of the anti-silicidation oxide layers, thus permitting subsequent silicidation of selected conductive regions within the circuitry.

REFERENCES:
patent: 4561170 (1985-12-01), Doering et al.
patent: 4871688 (1989-10-01), Lowrey
patent: 4945066 (1990-07-01), Kang et al.
patent: 4957878 (1990-09-01), Lowrey et al.

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