Method of making high speed semiconductor device having a silico

Details Method of making high speed semiconductor device having a silico Method of making high speed semiconductor device having a silico

1988-12-19

1990-06-12

Hearn, Brian E.

Fishing, trapping, and vermin destroying

437 29, 437 40, 437 57, 437 89, 437 99, 437173, 437228, H01L 2176, H01L 2195

Patent

active

049332988

ABSTRACT:
A CMOS silicon-on-insulation structure is fabricated by first forming an insulating SiO.sub.2 layer on a silicon substrate having a (110) plane. Openings are then formed in the SiO.sub.2 layer to expose a part of the substrate, and a polycrystalline or an amorphous silicon layer is deposited on the SiO.sub.2 layer and in the openings. The deposited silicon layer is divided into islands so that a first island includes one of the openings and a second island does not include any openings. A laser beam is then irradiated onto the islands so as to melt the islands, and when the laser light irradiation is discontinued, the melted islands recrystallize so that the first island forms a (110) plane and the second island forms a (100) plane. A p-channel MOSFET is fabricated on the first island, and an n-channel MOSFET is fabricated on the second island. The thus paired CMOS operates at high speeds, because the p-channel MOSFET using positive holes as the carrier is fast in a (110) crystal, and the n-channel MOSFET using electrons as the carrier is fast in a (100) crystal.

REFERENCES:
patent: 3745072 (1973-07-01), Scott, Jr.
patent: 3791024 (1974-02-01), Boleky, III
patent: 4412868 (1983-11-01), Brown et al.
patent: 4566914 (1986-01-01), Hall
patent: 4615762 (1986-10-01), Jastrzebski et al.
patent: 4768076 (1988-08-01), Aoki et al.

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