Semiconductor module having multiple insulation and wiring layer

Electricity: electrical systems and devices – Housing or mounting assemblies with diverse electrical... – For electronic systems and devices

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174252, 174 35R, 257700, 257713, 257723, 361717, 361718, 361719, 361720, 361761, 361762, 361783, 361792, 361794, 361795, H05K 118, H05K 720, H01L 2334

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055637736

ABSTRACT:
A memory IC having an SOJ type package is mounted on a metal wiring layer on the surface of the outer layer of a multilevel interconnection board. Protecting portions are formed on the package of the memory IC. The protecting portions contact the surface of the metal wiring layer when the memory IC is mounted on the multilevel level interconnection board. The shape of the projecting portions can be of various types, e.g., circular cylinders or prisms. Heat generated within the memory IC is transmitted to the metal wiring layer through the projecting portions. A first insulating layer has first and second surfaces. Wiring layers are formed on each of the first and second surfaces of the first insulating layer, and first and second semiconductor chips are connected to those wiring layers. First and second resin layers cover the whole surface of the outermost wiring layers and the first and second semiconductor chips.

REFERENCES:
patent: 3649950 (1972-03-01), Gluntz
patent: 4809058 (1989-02-01), Funamoto et al.
patent: 4973799 (1990-11-01), Soma et al.
patent: 5241456 (1993-08-01), Marcinkiewicz et al.
patent: 5258649 (1993-11-01), Tanaka et al.
patent: 5285352 (1994-02-01), Pastore et al.
patent: 5371653 (1994-12-01), Kametani et al.
IBM Technical Disclosure Bulletin "Plane Electrical Enhancement" vol. 32 No. 10A Mar. 1990.

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