Multilevel masterslice LSI with second metal level programming

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357 40, 357 45, 357 68, H01L 2348

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045009066

ABSTRACT:
A semiconductor device comprising a semiconductor bulk in which a plurality of basic circuit elements are formed, first interconnecting lines being formed on a first insulation layer of said semiconductor bulk, a second insulation layer formed on both said first insulation layer and said first interconnecting lines, and a cell in which said basic circuit elements are connected with each other by said first interconnecting lines, wherein the first interconnecting line for connecting two of said basic elements in the cell has two separated parts, one end of each of said parts is connected to one of said basic elements, said second insulation layer is provided with a pair of through-holes in the cell, and each of said pair of through-holes contacts with the other end of each of said parts.

REFERENCES:
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patent: 3641661 (1972-02-01), Canning et al.
patent: 3721838 (1973-03-01), Brickman et al.
patent: 3808475 (1974-04-01), Buelow et al.
patent: 4207556 (1980-06-01), Sugiyama et al.
Okabe et al., Electronics and Communications in Japan, vol. 55-C, No. 11, pp. 78-85, (1972).
Puri, IBM Tech. Discl. Bulletin, vol. 19, No. 7, Dec. 1976, pp. 2630-2631.

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