High speed comparator having controlled hysteresis

Details High speed comparator having controlled hysteresis High speed comparator having controlled hysteresis

1986-02-19

1987-06-02

Zazworsky, John

Electrical transmission or interconnection systems

Personnel safety or limit control features

Interlock

307359, 307362, H03K 524

Patent

active

046706712

ABSTRACT:
A high speed two micron CMOS comparator uses an input differential stage having feedback current mirror loads providing high speed current signals to an output cascode stage. Current mirror arrangement provide fast signal propagation through the comparator. Hysteresis is established by the output of the comparator positively fedback through a similar feedback differential stage superimposing controlled current signals into the cascode stage. Hysteresis of the output signal respecting a differential input signal is controlled by the ratio of bias currents of internal current sources which ratio is relatively insensitive to temperature changes.

REFERENCES:
patent: 4335358 (1982-06-01), Hoeft
patent: 4602168 (1986-07-01), Single
B. J. Hosticka, "Dynamic Amplifiers in CMOS Technology", Electronics Letters, vol. 15, No. 25, Dec. 6, 1979, pp. 814-820.

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