MOS transistor circuit for shared precharging of bus lines

Details MOS transistor circuit for shared precharging of bus lines MOS transistor circuit for shared precharging of bus lines

1985-07-19

1987-06-02

Heyman, John S.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307468, 307481, 365203, 377 57, G11C 700, G11C 1140

Patent

active

046706666

ABSTRACT:
An MOS transistor circuit for precharging parasitic capacitances C.sub.1 -C.sub.8 associated with a plurality of parallel data transfer bus lines 1-8 under the control of a clock signal .phi.. Each bus line is pulled up to an "H" state through associated MOS transistors T.sub.1 -T.sub.8, and only selected bus lines are thereafter pulled down to the "L" state pursuant to a bit transfer operation. The circuit is also provided with a series of MOS transistors T.sub.11 -T.sub.17 coupled across the adjacent bus lines such that the precharging of the discharged bus lines is contributed to by charging paths associated with non-discharged lines, to thereby shorten the overall precharging time and equalize the charge potentials.

REFERENCES:
patent: 3848236 (1974-11-01), Troutman
patent: 4458336 (1984-07-01), Takemae
patent: 4495602 (1985-01-01), Sheppard

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