Typewriting machines – Typing by other than type-face or type-die – Character formation by impact
Patent
1989-07-21
1991-07-09
Burr, Edgar S.
Typewriting machines
Typing by other than type-face or type-die
Character formation by impact
4001572, 101 9314, B41J 227, B41J 2235
Patent
active
050300202
DESCRIPTION:
BRIEF SUMMARY
FIELD OF THE INVENTION
The present invention relates to a wire-dot impact printer capable of printing by striking a printing wire provided at a wire-dot printing head onto a printing medium, especially to a wire-dot impact printer adapted for high quality printing.
BACKGROUND OF THE INVENTION
There is illustrated in FIG. 1 a construction of this type of wire-dot impact printer adopted conventionally. In the same figure, designated at 100 is a centro I/F, 101 is a CPU, 102 is I/O LSI as an interface, 103 is a timer, 104 is a head driver, 105 is a wire-dot head, 106 is an operation switch, 107 is a line feed motor, 108 is a spacing motor. In the apparatus, the CPU 101 receives a printing date via the centro I/F 100 and supplies a control signal issued on the basis of the printing data to the timer 103, the head driver 104, the line feed motor 107 and the spacing motor 108 via the I/O LSI 102. The head driver 104 receives a control signal from the CPU 101 and a drive timing signal from the timer 103 for driving the wire-dot printing head 105 to effect printing.
As the wire-dot printing head 105, there is an arrangement as illustrated in FIG. 2. In the same figure, designated at 110 are a plurality of printing wires (two printing wires are illustrated in the same figure) provided in the wire-dot printing head 105, 111 is a guide frame having a guide groove llla, 112 is an armature for supporting the printing wires 110, and 113 is a plate spring for supporting the armature 112. Hereupon, designated at 114 is a base plate, 115 is an electromagnet composed of a core 115a and a coil 115b wound around the core 115a, 116 is a permanent magnet, 117 is a rack, 118 is a spacer, 119 is a yoke, and 120 is a clamp. The clamp 120 presses and holds the base plate 114, the permanent magnet 116, the rack 117, the spacer 118, the plate spring 113, the yoke 119, the front cover 111 in a manner such that each of these members are laid one over another in turn and integrated.
The armature 112 is supported at the side of a free end 113a of the plate spring 113 while a base end 110a of one of the printing wires 100 is fixedly mounted on a distal end 112a of the armature 112. A distal end 110b of the printing wire 110 is guided by the guide groove 111a of the guide frame 111 so as to strike a predetermined position of the printing paper (not shown).
With the arrangement as set forth above, when the coil 115b of the electromagnet 115 is deenergized, the armature 112 is attracted to the side of the base plate 114 (downward direction in the figure) by the attraction force of the permanent magnet 116 against the resilience force of the plate spring 113. When the coil 115b is energized, a magnet flux of the permanent magnet 116 is cancelled by the magnet flux of the electromagnet 115 to release the armature 112 from the attraction force of the permanent magent 116 to move the armature 112 toward the side of the guide frame 111 (upward direction in the same figure) by the resilience force of the place spring 113. At the same instant, the printing wire 110 provided at the armature 112 moves toward the side of the guide frame 111 and the distal end 110b thereof projects over the guide slit 111a and strikes the printing paper to effect printing.
FIG. 3 is a circuit diagram of the timer 103 and FIG. 4 is a waveform diagram of the operation of the timer circuit 103. The timer 103 is a portion to adjust an optimum time for energizing the coil 115b on the basis of the voltage to be applied to the coil 115b.
In the same figure, designated at 120 is an open-collector type NOT circuit, 121, 122, 123 are resistors, 124 is a diode, 125 is a capacitor, and 126 is a comparator. The timer circuit 103 operates as follows. Firstly, a signal tl received from the I/O LSI 102 is applied to the NOT circuit 120 on the basis of the instruction from the CPU 101. The signal, t1 becomes high level (5 V) during the period of T1 as illustrated in FIG. 4. At the time when the signal t1 is in high level, an output of the NOT circuit 120 becomes low level (0 V) whe
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patent: 3872788 (1975-03-01), Palombo
patent: 4347786 (1982-09-01), Sweat, Jr. et al.
patent: 4440079 (1984-04-01), Dayger et al.
patent: 4468140 (1984-08-01), Harris
patent: 4597328 (1986-07-01), Carrington et al.
patent: 4844635 (1989-07-01), Malkemes et al.
Ishimizu Hideaki
Kikuchi Hiroshi
Komori Chihiro
Tanuma Jiro
Burr Edgar S.
Keating Joseph R.
OKI Electric Industry Co., Ltd.
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