1981-12-30
1984-08-07
Atkinson, Charles E.
Excavating
G06F 1110
Patent
active
044647530
DESCRIPTION:
BRIEF SUMMARY
BACKGROUND OF THE INVENTION
The present invention relates to error correcting codes (ECC's) for the correction of packaging errors in memory arrays. More particularly, the present invention relates to ECCs for the correction of all failures of a single monolithic memory chip and the detection of all failures of two such chips in a memory where each of the monolithic chips contains 2 bits from a single word.
From an error correction standpoint, it is highly desirable that semiconductor memory systems be organized on a bit per chip basis. In a memory with this type of organization 72 chips would be required to store a 72 bit codeword with each bit of the word on a different chip. The advantage of using one bit per chip memory organization is that a single error correction/double error detection (SEC/DED) error correcting code (ECC) can be used to correct errors when there is a total failure of a chip.
A disadvantage of the one bit per chip organization is that it consumes more electrical power than a multibit per chip organization since there are more chips needed to form an ECC codeword and each of the chips must be powered up when the memory is assessed. Therefore, ECC codes that correct single errors and detect double errors caused by both bit and package failures in a memory organized on a multibit per chip basis are highly desirable.
Single error correction/double error detection (SEC/DED) codes for detecting package errors are shown in U.S. Pat. No. 4,077,028. The problem with these codes is that they do not correct for package errors.
A b-adjacent code of the type described in Bossen U.S. Pat. No. 3,634,821 assigned to the assignee of the present invention can be adapted to correct the failure of a single multibit package and detect failure of two multibit packages by the addition of an additional check symbol. The problem with using a b-adjacent code is the large number of check bits required to do the detecting and correcting. Three ECC check bit bytes are necessary in order to correct a one byte error and detect a two byte error using such a b-adjacent code. The number of bytes n correctable by the code is equal to n=2.sup.b +2. Thus, for a two bit byte n=6. Since three of the six bytes are ECC check bit bytes only three of the bytes would be data bit bytes.
Another way to correct all single package errors and detect all double package errors, would be to adopt Reed-Solomon codes. Such a technique is described in an article by Kaneda and Fujiwara entitled "Single Byte Error Correcting--Double Byte Error Detecting Codes for Memory Systems" on pages 41 to 46 of the Proceedings of the 10th Fault Tolerant Computing Symposium held on Oct. 1-3, 1980. In the article, an existing Reed-Solomon packaged error correcting code is expanded to generate a longer code length package error correcting code which makes efficient use of check bits. While the general catagory of this generalized code makes of efficient use of check bits, those described as being modularized are no so efficient.
Therefore, it would be desirable to provide a new modularized code that makes efficient use of the number of correction bits needed to correct single package errors and detect double package errors where the package errors can be one or more bits in error.
THE INVENTION
In accordance with the present invention, encoding means is provided for encoding data words into code words in which the exclusive OR of all single bit error syndromes in any convenient package results in a composite syndrome which is unique in each package. This code is a single error detection double error correction code which has been expanded to cover m bits where m is equal to the number of bits in the package.
Therefore, it is an object of the present invention to provide a new code to correct single and double bit errors and at the same time correct single package errors and detect double package errors.
It is another object of the present invention to correct single package errors and detect double package errors with less check bits than required p
REFERENCES:
patent: 3634821 (1972-01-01), Bossen et al.
patent: 4077028 (1978-02-01), Lui et al.
patent: 4319357 (1982-03-01), Bossen
patent: 4358848 (1982-11-01), Patel
Bossen et al., Measurement and Generation of Error Correcting Codes for Package Failures, IEEE Transactions on Computers, vol. C-27, No. 3, Mar. 1978, 201-204.
W. H. Cochran and W. A. Lopour, IBM Technical Disclosure Bulletin, Optimized Error Correction/Detection for Chips Organized Other Than By-1, vol. 24, No. 10, Mar. 1982, 5275-6.
Atkinson Charles E.
International Business Machines - Corporation
Jablon Clark A.
Murray James E.
LandOfFree
Two bit symbol SEC/DED code does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Two bit symbol SEC/DED code, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Two bit symbol SEC/DED code will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-606294