Memory address control apparatus with separate translation look

Details Memory address control apparatus with separate translation look Memory address control apparatus with separate translation look

1986-12-24

1988-02-23

Zache, Raulfe B.

Boots, shoes, and leggings

G06F 1202

Patent

active

047274840

ABSTRACT:
A memory control apparatus for a data processor using a virtual memory technique includes two cache memories one for storing a portion of the instructions located in the main memory (MMU), the other for storing a portion of the operand data located in main memory. A separate translation look aside buffer (TLB) is connected to each cache memory, with the TLB connected to the cache memory storing instructions operating to translate logical addresses to real addresses in the MMU storing instructions, while the TLB connected to the cache memory storing operand data operating to translate logical addresses to real addresses in the MMU storing operand data.

REFERENCES:
patent: 4355355 (1982-10-01), Butwell et al.
patent: 4464712 (1984-08-01), Fletcher
patent: 4500952 (1985-02-01), Heller et al.
patent: 4502110 (1985-02-01), Saito
patent: 4612612 (1986-08-01), Woffinden et al.
patent: 4638426 (1987-01-01), Chang et al.

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