Small dimension field effect transistor using phosphorous doped

Details Small dimension field effect transistor using phosphorous doped Small dimension field effect transistor using phosphorous doped

1983-11-03

1985-02-19

Hearn, Brian E.

Metal working

Method of mechanical manufacture

Assembling or joining

29578, 29590, 148 15, 427 93, H01L 2194

Patent

active

044996535

ABSTRACT:
A process for fabricating semiconductor devices including a field effect transistor has been described incorporating a substrate, a layer of thermal oxide having windows, a layer of polycrystalline silicon to form the gate electrode of field effect transistors and a first interconnection layer, a layer of silicon nitride, a layer of phosphorous doped silicon dioxide which have windows larger than the device windows and which is reflowed to smooth its upper surface over the polysilicon interconnections and to provide round edges, impurity regions formed on either side of the silicon gate electrode and bounded by the thermal oxide, forming openings to the drain and source regions, depositing a layer of metal over the substrate and defining the layer of metal to form a second layer of interconnections and also to provide ohmic contact to the source and drain regions. The process overcomes the problem of forming openings through a layer of phosphorous doped silicon oxide and further overcomes the problem of subsequent out diffusion of a drain and source impurity region at times when a layer of phosphorous doped silicon oxide is reflowed thus permitting shallow drain and source regions for short channel field effect transistors.

REFERENCES:
patent: 3739237 (1973-06-01), Shannon
patent: 3887733 (1975-03-01), Tolliver et al.
patent: 4191603 (1980-03-01), Garbarino et al.
patent: 4204894 (1980-05-01), Komeda et al.
patent: 4261765 (1981-04-01), Komatsu et al.
patent: 4348802 (1982-09-01), Shirato

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