Poly-sidewall contact transistors

Details Poly-sidewall contact transistors Poly-sidewall contact transistors

1987-06-03

1988-08-16

Carroll, J.

357 34, 357 49, 357 54, 357 65, H01L 2904, H01L 2972, H01L 2712, H01L 2348

Patent

active

047648015

ABSTRACT:
Improved semiconductor devices having minimum parasitic junction area are formed by using multiple buried polycrystalline conductor layers to make lateral contact to one or more pillar-shaped epitaxial single crystal device regions. The lateral poly contacts are isolated from each other and from the substrate and have at least one polycrystalline pillar extending to upper surface of the device to permit external connections to the lowest poly layer. The lateral epi-poly sidewall contacts are recessed under the intervening oxide layers to separate them from the active device regions in the center of the epi pillar. The structure is made by depositing three dielectric layers with two poly layers sandwiched in between. Holes are anisotropically etched to the lowest poly layer and the substrate. The exposed edges of the poly layers are oxidized. These edge oxide regions are removed in the holes where the device pillars are epitaxially grown. The remaining edge oxide regions isolate the buried conductor layers, contacts, and isolation walls. The polycrystalline pillar extending from the lowest poly layer to the device surface is formed at the same time as the epi-pillar. The structure is self-aligned and self-registering.

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