Plugged poly silicon resistor load for static random access memo

Details Plugged poly silicon resistor load for static random access memo Plugged poly silicon resistor load for static random access memo

1986-07-30

1988-02-23

Chaudhuri, Olik

Fishing, trapping, and vermin destroying

437 57, 437 60, 437190, 437192, 437193, 357 59, 148DIG136, H01L 2182, H01L 2190

Patent

active

047270454

ABSTRACT:
An improved process for fabricating a static RAM cell having a polysilicon load resistance is provided. Following formation of source, gate and drain regions, a planarized dielectric structure is formed over the junction regions, and via openings which expose portions of the source and drain regions are created. The via openings are filled with polysilicon interconnects, appropriately doped for low resistance contacts. Where the contact includes a resistor load, the polysilicon is not doped. Thus, the prior art approach of providing doped and undoped regions along the same polysilicon interconnect is not employed. Rather, the doped and undoped regions are physically separated. Consequently, the minimum length of the poly load is limited only by the ability to form via openings of small dimensions.

REFERENCES:
patent: 4210465 (1980-07-01), Brower
patent: 4271424 (1981-06-01), Inayoshi et al.
patent: 4292730 (1981-10-01), Ports
patent: 4416049 (1983-11-01), McElroy
patent: 4640004 (1987-02-01), Thomas et al.

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