Programmable logic device with internal time-constant multiplexi

Details Programmable logic device with internal time-constant multiplexi Programmable logic device with internal time-constant multiplexi

1993-06-18

1997-07-01

Trans, Vincent N.

Boots, shoes, and leggings

326 39, 326 41, H03K 17693, H03K 19177

Patent

active

056444966

ABSTRACT:
A method and on-chip architecture are disclosed for multiplexing signals from selected external interconnect buses to chip internal buses such that bus rerouting can be implemented programmably without substantially affecting timing relations between time-parallel signals of a rerouted bus. An on-chip switch matrix is provided having N input lines crossing with M output lines to provide N times M crosspoints. A plurality of substantially less than N times M programmable interconnect switches (PIP's) are distributed symmetrically among the N.multidot.M crosspoints such that a same first number of interconnect switches (PIP's) are found along each of the N input lines thereby providing equal loading on each input line. The plurality of programmable interconnect switches (PIP's) are further distributed among the N.multidot.M crosspoints such that a same second number of interconnect switches (PIP's) are found along each of the M output lines thereby providing equal loading on each output line.

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