Fishing – trapping – and vermin destroying
Patent
1987-11-23
1988-08-16
Ozaki, George T.
Fishing, trapping, and vermin destroying
437 31, 437 41, 437 59, H01L 21425
Patent
active
047644826
ABSTRACT:
A method for fabricating an integrated circuit including at least one metal-oxide-semiconductor transistor (MOS) and at least one bipolar transistor is disclosed. The pocket regions used to reduce the short channel effect in the MOS transistor are formed simultaneously with the base region for the bipolar transistor.
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Davis Jr. James C.
General Electric Company
Ozaki George T.
Steckler Henry I.
Webb II Paul R.
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