Digitally controlled capacitive load

Details Digitally controlled capacitive load Digitally controlled capacitive load

1996-03-21

1997-07-01

Callahan, Timothy P.

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Having specific delay in producing output waveform

327264, 327288, H03K 513, H03K 1728

Patent

active

056442629

ABSTRACT:
An integrated circuit for selectively providing delay to a waveform carried on a signal line. With the present invention, a waveform is carried by a signal line to which a digitally-controlled capacitive load is coupled. A digital enable line is directly coupled to the capacitive load which either activates or deactivates the capacitive load. When the enable line is in the active state, the capacitive load is activated and the load therefore has maximum capacitance. Accordingly, the delay of the waveform carried on the signal line is also maximized. When the enable line is in the inactive state, the capacitive load has minimal capacitance and the delay of the signal being carried on the signal line is therefore minimized.

REFERENCES:
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patent: 4975605 (1990-12-01), Bazes
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patent: 5416436 (1995-05-01), Rainard
"A Novel CMOS Digital Clock and Data Decoder", Mel Bazes & Roni Ashuri, IEEE Journal of Solid-State Circuits, vol. 27, No. 12, Dec. 1992, pp. 1934-1940.

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