CMOS pulse delay circuit

Details CMOS pulse delay circuit CMOS pulse delay circuit

1993-07-21

1995-10-17

Callahan, Timothy P.

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Having specific delay in producing output waveform

327288, H03K 5159

Patent

active

054594243

ABSTRACT:
A CMOS pulse delay circuit is arranged to accurately delay an input pulse signal by a predetermined period. The CMOS pulse delay circuit provides two inverters for causing delays. The inverters each have switching transistors. The switching transistors of the first inverter are associated with voltage-controllable variable resistance elements located in series to each other for varying the on-resistance of the transistors. The varying of the on-resistance results in keeping the output delay phases accurate.

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patent: 5159205 (1992-10-01), Gorecki et al.
patent: 5231319 (1993-07-01), Crafts et al.
patent: 5239213 (1993-08-01), Norman et al.
patent: 5287025 (1994-02-01), Nishimichi

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