Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Of specified material other than unalloyed aluminum
Patent
1995-01-05
1995-10-17
Mintel, William
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
Of specified material other than unalloyed aluminum
257759, 257760, 257763, 257764, 257765, 257915, H01L 2943
Patent
active
054593530
ABSTRACT:
A first interlayer dielectric film layer is formed on a P-type semiconductor substrate. The first interlayer dielectric film is made of a BPSG film formed by the method of atmospheric pressure chemical vapor deposition. First connection holes are formed at specified positions of the first interlayer dielectric film layer. A first conductive film layer is formed in a region including at least the first connection holes. The first conductive film layer is composed of three layers by sequentially laminating a barrier metal film, an aluminum alloy film, and an anti-reflection film. On the first conductive film layer formed in a specified pattern, a second interlayer dielectric film layer is formed. The second interlayer dielectric film layer is composed of a lower layer of silicon oxide film, an intermediate layer of silicon oxide film made of inorganic silica or organic silica, and an upper layer of silicon oxide film. Specified positions of the second interlayer dielectric film layer are selectively removed. The removed regions become second connection holes. A second conductive film layer is formed thereon. The second conductive film layer is composed of two layers of refractory metal film in the bottom layer and aluminum alloy film in the top layer.
REFERENCES:
patent: 4107726 (1978-08-01), Schilling
patent: 4357203 (1982-11-01), Zelez
patent: 4910580 (1990-03-01), Kuecher et al.
patent: 4924295 (1990-05-01), Kuecher
patent: 4942451 (1990-07-01), Tamaki et al.
patent: 5040049 (1991-08-01), Raaijmakers
patent: 5117273 (1992-05-01), Stark et al.
patent: 5136362 (1992-08-01), Grief et al.
Patent Abstracts of Japan, Kokai #01-241149 to Michio, Sep. 1989, Abstract vol. 013574, Group E-863.
Patent Abstracts of Japan, Kokai #02-235372 to Tatsuro, Sep. 1990, Abstract vol. 014550, Group E-1009.
Patent Abstracts of Japan, Kokai #01-266746 to Hiroyuki, Oct. 1989, Abstract vol. 014032, Group E-876.
N. Kumar et al., "Thin Solid Films", Oct. 1988, pp. 417-428, Failure Mechanisms of TiN Thin Film Diffusion Barriers.
A. S. Bhansali et al, "Journal of Applied Physics", Aug. 1990, pp. 1043-1049, A Thermodynamic Approach for interpreting metallization layer stability and thin-film reactions involving four elements: Application to integrated circuit metallurgy.
Y. Takata et al., "A Highly Reliable Multilevel Interconnection Process for 0.6 .mu.m CMOS Devices", IEEE VLSI Multiplevel Interconnection Conference, Eighth International Proceedings, IEEE Catalog No. 91TH0359-0, pp. 13-19, Jun. 11-12, 1991.
Brown Peter Toby
Matsushita Electronics Corporation
Mintel William
LandOfFree
Semiconductor device including interlayer dielectric film layers does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Semiconductor device including interlayer dielectric film layers, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor device including interlayer dielectric film layers will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-599629