Patent
1995-05-24
1998-03-31
Coleman, Eric
395513, G06F 1700
Patent
active
057348081
DESCRIPTION:
BRIEF SUMMARY
TECHNICAL FIELD
This invention relates to a pipeline processing device as well as to a clipping processing device, a three-dimensional (3D) simulator device, and a pipeline processing method using such a pipeline processing device.
BACKGROUND OF ART
In the prior art, since real-time processing must be performed by a 3D simulator device, such as a 3D simulator device used in a video game or piloting simulator for an aircraft or any of various other types of vehicle that displays pseudo-3D images, data processing is generally performed by a method called pipeline processing.
In this case, pipeline processing is a data processing method in which function-specific hardware is connected in series and the processing load is equalized between these components.
Processing devices using two methods, clock-driven pipeline processing and data-driven pipeline processing, are known as prior-art pipeline processing devices as shown in FIGS. 20A and 20B.
With the clock-driven pipeline processing device shown in FIG. 20A, registers 450 to 453 driven by a common clock signal are connected in series, and data processing is performed thereby in data processing sections 455 to 458. This clock-driven pipeline processing device has the advantage that, since the entire flow of the data to be processed is synchronized by this common clock signal and is at the same timing, the control method is extremely simple.
With the data-driven pipeline processing device shown in FIG. 20B, registers 460 to 463 that are driven only if there is processing data in the previous stage are connected in series, and data processing is performed thereby in data processing sections 465 to 468. In this data-driven pipeline processing device, each of the registers 460 to 463 is driven only if there is processing data in the previous stage. Therefore, there must be processing data in all of the registers during the execution of pipeline processing. As a result, equalization of the load of data processing, which is an objective of pipeline processing, can be implemented even more efficiently.
However, both the above described clock-driven pipeline processing device and data-driven pipeline processing device have problems, as described below.
With the clock-driven pipeline processing device, a common clock signal is supplied to all of the registers 450 to 453 and the processing data is transferred thereby. This means that the transfer of processing data will continue, even if there is no processing data in the previous-stage register. As a result, if there is a register to which processing data has not been input, the presence of a register without processing data is noted during the pipeline processing, and it becomes impossible to implement equalization of the load of data processing, which is the objective of pipeline processing.
The description now turns to the data-driven pipeline processing device, but first deals with the defect that the control and configuration methods thereof are not very simple. In other words, the device of this method must be provided with a control circuit for controlling the flow of processing data such that it proceeds onward only if there is processing data in the previous stage. However, when such a control circuit is provided, decisions as to what configuration and control method to use are not easy problems to solve. To ensure that this control circuit can be connected to all the registers 460 to 463 and reduce the load on the hardware, it is necessary to make the configuration thereof as simple as possible and reduce the number of circuits, but these points cause major technical problems.
The flow of a data-driven pipeline processing device can only proceed forward if there is data in the previous stage. Therefore, processing data in the register 461 can only be transferred to the data processing sections 466, 667, and 468 and the registers 462 and 463 of the next stages if there is processing data in the register 460. Therefore, if the need arises to transfer data from the register 461 to the next stage, regardless
REFERENCES:
patent: 4449201 (1984-05-01), Clark
patent: 4945500 (1990-07-01), Deering
patent: 5208909 (1993-05-01), Corona
patent: 5297240 (1994-03-01), Priem
patent: 5420980 (1995-05-01), Pineda
Coleman Eric
Namco Ltd.
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