Fast summing circuit

Details Fast summing circuit Fast summing circuit

1988-06-14

1989-11-28

Clark, David L.

Boots, shoes, and leggings

G06F 750

Patent

active

048842338

ABSTRACT:
A summing circuit (20) is for summing up zeroth through n-th input data signals A(0) to A(n) to produce a sum signal S consisting of zeroth through m-th output bits s(0) to s(m) where n represents a first predetermined natural number and m represents a second predetermined natural number which is not less than the first predetermined natural number. A preprocessing circuit (22) preprocesses the zeroth through the n-th input data signals A(0) to A(n) into a preprocessed signal which is (n+1) bits long. A logic circuit (24) carries out a logical operation on the preprocessed signal to produce the sum signal S. For example, each of the zeroth through the n-th input data signals A(0) to A(n) is given by an equation: ##EQU1## where a(d) represents a d-th coefficient having one of logic zero and one values, k represents a predetermined integer which is not less than zero, and A represents a common coefficient having the logic zero value. Each of the zeroth through the n-th input data signals A(0) to A(n) may be given by another equation: ##EQU2## where p(d)'s represent zeroth through n-th discrete integers.

REFERENCES:
patent: 4041296 (1977-08-01), Dauby et al.
patent: 4598382 (1986-07-01), Sato
C. S. Wallace, "A Suggestion for a Fast Multiplier*" IEEE Transactions on Electronic Computers, Feb. 1987, pp. 14-17.

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