Patent
1988-08-05
1989-11-28
Hille, Rolf
357 80, 357 68, H01L 2312, H01L 2314
Patent
active
048841226
ABSTRACT:
The utilization of a removable overlay layer together with its associated metalization pattern, is used to effectively provide wafer scale integration for integrated circuit chips. The method and configuration of the present invention provide for the fabrication and testing of systems which are otherwise untestable. The present invention also permits integrated circuit systems to be tested in their final configuration in terms of speed and operating environment and the invention eliminates many of the problems associated with wafer or chip probes. The present invention also utilizes special test chips which are either temporarily or permanently affixed in an integrated circuit chip package.
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The STD Process-New Development and Applications-Clark et al.-pp. 131-144, 1974, International Microwave Symposium.
Eichelberger Charles W.
Welles II Kenneth B.
Wojnarowski Robert J.
Clark S. V.
Davis Jr. James C.
General Electric Company
Hille Rolf
Ochis Robert
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