Integrated circuit and method for low noise frequency synthesis

Details Integrated circuit and method for low noise frequency synthesis Integrated circuit and method for low noise frequency synthesis

1999-05-06

2000-08-22

Grimm, Siegfried H.

Oscillators

Automatic frequency stabilization using a phase or frequency...

With reference oscillator or source

331 1A, 331 25, H03L 708

Patent

active

061078913

ABSTRACT:
An integrated circuit device and method for synthesis of a signal having a desired frequency and low noise. The integrated circuit embodiment of the invention generally includes a phase locked loop (PLL) circuit used in conjunction with a frequency multiplier. Specifically, the integrated circuit embodiment includes a frequency multiplier connected to a first input of a phase detector, a low pass filter connected between the output of the phase detector and the input of a voltage controlled oscillator (VCO), and a frequency divider connected between the output of the VCO and a second input to the phase detector. The frequency multiplier produces a signal having a frequency that is a multiple of the frequency of a reference signal which is connected to the input of the frequency multiplier. For any desired output frequency, use of the multiplier results in a smaller divider ratio "n" in the PLL, thereby reducing the closed loop noise inside the PLL loop bandwidth. Other embodiments of the invention include a method for low noise frequency synthesis, and a method of low noise frequency synthesis for clocking data onto a SONET OC-48 channel. The invention provides the advantage of frequency synthesis with low noise.

REFERENCES:
patent: 4940950 (1990-07-01), Helfrick
patent: 4965533 (1990-10-01), Gilmore
patent: 5317284 (1994-05-01), Yang
patent: 5420545 (1995-05-01), Davis et al.
patent: 5764111 (1998-06-01), Bushman
patent: 6028460 (2000-02-01), McCollum et al.

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