Semiconductor device having interconnection and adhesion layers

Details Semiconductor device having interconnection and adhesion layers Semiconductor device having interconnection and adhesion layers

1998-03-16

2000-08-22

Chaudhuri, Olik

Active solid-state devices (e.g., transistors, solid-state diode

Combined with electrical contact or lead

Of specified material other than unalloyed aluminum

257763, 257751, 257753, H01L 2348, H01L 2352, H01L 2940

Patent

active

061076872

ABSTRACT:
A Cu interconnection layer is formed in a trench provided in an insulating layer with a base layer interposed therebetween, an adhesion layer is formed on the Cu interconnection layer and a cap layer is formed on the adhesion layer to restrict exfoliation of the cap layer formed on the Cu interconnection layer buried in the trench formed in the insulating layer.

REFERENCES:
patent: 4961822 (1990-10-01), Liao et al.
patent: 5470792 (1995-11-01), Yamada
patent: 5592024 (1997-01-01), Aoyama
patent: 5700737 (1997-12-01), Yu et al.
patent: 5717250 (1998-02-01), Schuele et al.
"Metal Capped Cu Interconnection Technology . . . ", T. Mori, et al., 1996 VLSI Multilevel Interconnection Conference, Santa Clara, California.
"Interconnection Process Employing Damascene Method" H. Shibata, Semiconductor World (monthly issued), Dec. 1995, pp. 179-184.
"Damascene Cu Interconnection Capped by TiWN Layer", T. Fukada, Shingakugiho Technical Report of IEICE. SDM96-169, Dec. 1996, pp. 85-92.

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