Active solid-state devices (e.g. – transistors – solid-state diode – Integrated circuit structure with electrically isolated... – Including dielectric isolation means
Patent
1997-08-28
2000-08-22
Jackson, Jr., Jerome
Active solid-state devices (e.g., transistors, solid-state diode
Integrated circuit structure with electrically isolated...
Including dielectric isolation means
257315, 257640, 257760, H01L 29788, H01L 21762, H01L 2951
Patent
active
061076708
ABSTRACT:
Disclosed is a contact structure between the bit line and the source/drain region in an EEPROM. An element region is isolated by a trench type element isolation region in a silicon substrate. The source/drain region is formed in the portion of the element region, that is surrounded by the trench type element isolation region and a multilayered gate. A silicon nitride film covers the surface of the trench type element isolation region and that of the multilayered gate, and an interlevel insulating film made from silicon dioxide is formed. A contact hole is formed in the interlevel insulating film. The source/drain region and the silicon nitride film are exposed in the contact hole. A bit line is connected to the source/drain region through the contact hole.
REFERENCES:
patent: 5324974 (1994-06-01), Liao
patent: 5734607 (1998-03-01), Sung
Jackson, Jr. Jerome
Kabushiki Kaisha Toshiba
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