Low power dual-mode CMOS bias voltage generator

Details Low power dual-mode CMOS bias voltage generator Low power dual-mode CMOS bias voltage generator

1987-12-02

1989-11-28

Heyman, John S.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307443, 307452, 3072965, H03K 301, H03K 19003, H03K 19096

Patent

active

048839760

ABSTRACT:
A substrate voltage bias generator is disclosed including a charge pump whose output is clamped during charge pump capacitor charging cycles to zero volts thereby eliminating a voltage drop associated with prior art clamping diodes. The charge pump further includes a stand-by and booted mode, the stand-by mode providing a first level of output current at a specified generated substrate bias voltage and in the booted mode generating increased output current and voltage. The increased voltage is generated across the charge pump capacitor by a second capacitor that is only operative in the booted mode and whose charge is shared with the charge pump capacitor thereby developing a higher voltage across the charge pump capacitor. The output voltage generated by the substrate bias generator is detected and if it is too low a voltage, the booted mode is turned off. An external signal determines whether the stand-by mode or booted mode are selected.

REFERENCES:
patent: 4585954 (1986-04-01), Hashimoto et al.
patent: 4695746 (1987-09-01), Tobita

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