Refresh control system

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Details

365222, G06F 1300, G11C 700

Patent

active

041588835

ABSTRACT:
In a refresh control system including a main memory having a volatile memory, at least one processing unit for accessing the main memory, a memory bus for effecting signal transfer between the main memory and the processing unit and a supervision circuit for allotting use of the memory bus in response to a request signal, the refresh control system is characterized by a refresh control circuit for transferring the request signal to the supervision circuit at the time the refresh signal is required and for commanding the initiation of the refresh operation to the main memory in response to a grant signal from the supervision circuit.

REFERENCES:
patent: 3760379 (1973-09-01), Nibby, Jr. et al.
patent: 3800295 (1974-03-01), Anderson, Jr. et al.
patent: 3810129 (1974-05-01), Behman et al.

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