Decoder/comparator and method of operation

Details Decoder/comparator and method of operation Decoder/comparator and method of operation

1992-08-31

1994-03-01

Westin, Edward P.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307452, 307481, H03K 190948, H03K 19096

Patent

active

052910768

ABSTRACT:
A precharge device (28) has a first (30) and a second node (32), a transistor tree (29), a screening transistor (Q20) and clocking circuitry (Q17, Q18, Q19). The transistor tree (29) couples the first (30) and the second (32) node and is operable to electrically short-circuit the nodes according to input signals (A.sub.1, A.sub.2, A.sub.3). The screening transistor (Q20) has a first and a second [source-drain region] current electrode and a [gate] control electrode. The first [source-drain region] current electrode is coupled to a third node (34), the second [source-drain region] current electrode is coupled to the second node (32) and the [gate] control electrode is coupled to the first node (30). The clocking circuitry alternately precharges the first (30) and third nodes (34) to a first known voltage level and evaluates the voltage on the first node (30) to output a logic level.

REFERENCES:
patent: 4086500 (1978-04-01), Suzuki et al.
patent: 4401903 (1983-08-01), Iizuka
patent: 4567581 (1986-01-01), Dumbri et al.
patent: 5015882 (1991-05-01), Houston et al.
patent: 5065048 (1991-11-01), Asai et al.

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