Computer architecture capable of concurrent issuance and executi

Details Computer architecture capable of concurrent issuance and executi Computer architecture capable of concurrent issuance and executi

Filed on

1995-11-03

Date issued

1996-11-12

Examiner

Geckil, Mehmet B.

Patent Class

Boots, shoes, and leggings

Other Related Categories

395376, 395561, 364DIG1, 3642318, G06F 930

Type

Patent

Status

active

Patent number

055749410

Description

ABSTRACT:
A system for issuing a family of instructions during a single clock includes a decoder for decoding the family of instructions and logic, responsive to the decode result, for determining whether resource conflicts would occur if the family were issued during one clock. If no resource conflicts occur, an execution unit executes the family regardless of whether dependencies among the instructions in the family exist.

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IBM Technical Disclosure Bulletin, vol. 29, No. 2, Jul. 1986, pp. 605-608, "Data Bypass Methodology for a Performance Pipeline Processor".
Ramon D. Acosta et al., "An Instruction Issuing Approach to Enhancing Performance in Multiple Functional Unit Processors," IEEE Transactions on Computers, vol. C-35, No. 9, Sep. 1986, pp. 815-828.
Shlomo Weis et al., "Instruction Issue Logic in Pipelined Computers," IEEE Transactions on Computers, Nov. 1984, pp. 1013-1022.
Garold S. Tjaden et al., "Detection and Parallel Execution of Independent Instructions," IEEE Transactions on Computers, vol. C-19, No. 10, 10/70, pp. 889-895.

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