Computer graphics parallel system with temporal priority

Details Computer graphics parallel system with temporal priority Computer graphics parallel system with temporal priority

1993-09-29

1996-11-12

Tung, Kee Mei

395510, G06F 1516

Patent

active

055748473

ABSTRACT:
Front end processors in a graphics architecture execute parallel scan conversion and shading to process individually assigned primitive objects for providing update pixels. A crossbar along with groups of first-in-first-out registers (FIFOs) accommodates data flow to parallel pixel processors with associated memory capabilities (frame buffer banks) where visibility and blending operations are performed on predetermined sequences of update pixels to provide frame buffer pixels and ultimately display pixels. The pixel processors identify with sequences of pixels in the display in patterns designed to equalize processor loads for pixels located along scan lines of a raster, or distributed over an area. Update pixel data is tagged to identify FIFO groups (pixel processors) individual FIFO selection and output sequence. Temporal priority is accomplished so that primitive data is entered in the frame buffer banks (components) restored to the same order as generated at the central processor (CPU) level.

REFERENCES:
patent: 4918626 (1990-04-01), Watkins et al.
patent: 4949280 (1990-08-01), Littlefield
patent: 5315699 (1994-05-01), Imai et al.
patent: 5325485 (1994-06-01), Hochmuth et al.
patent: 5459835 (1995-10-01), Trevett
patent: 5465368 (1995-11-01), Davidson et al.
IEEE Computer Graphics and Applications, "Breaking the Frame Buffer Bottleneck with Logic Enhanced Memories", by Poulton et al, Nov. 1992. pp. 65-74.

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