Multiple bit encoding technique for combinational multipliers

Details Multiple bit encoding technique for combinational multipliers Multiple bit encoding technique for combinational multipliers

1982-07-01

1985-01-22

Shaw, Gareth D.

Boots, shoes, and leggings

G06F 750

Patent

active

044955936

ABSTRACT:
A four member encoding set is disclosed which allows the construction of combinational monolithic multipliers with a significant reduction in the number of devices required. The reduced device and wire count in the present technique allows a multiplier circuit of any given size to be made less expensively or alternatively allows a larger precision multiplier to be constructed.

REFERENCES:
patent: 4110832 (1978-08-01), Leininger et al.
patent: 4122527 (1978-10-01), Swiatowiec
A. Booth, "A Signed Binary Multiplication Technique", Quarterly Journal of Mechanics and Applied Mathematics, vol. IV, pt. 2, pp. 236-240, (1951).

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