Method of forming a bit line over capacitor array of memory cell

Details Method of forming a bit line over capacitor array of memory cell Method of forming a bit line over capacitor array of memory cell

1995-02-22

1996-10-08

Chaudhari, Chandra

Fishing, trapping, and vermin destroying

437 63, 437919, H01L 218242

Patent

active

055630898

ABSTRACT:
A semiconductor memory device includes, a) a semiconductor substrate; b) a field effect transistor gate positioned outwardly of the semiconductor substrate; c) opposing active areas formed within the semiconductor substrate on opposing sides of the gate; d) a capacitor electrically connected with one of the active areas; e) a bit line; f) a dielectric insulating layer positioned intermediate the bit line and the active areas; g) a bit line plug extending through the insulating layer and electrically interconnecting the bit line with the other active area, the bit line plug comprising an electrically conductive annular ring. Integrated circuitry, beyond memory devices, utilizing an annular interconnection ring are also disclosed. Such constructions having additional radially inward insulating annular rings and conductive rings are also disclosed. A method of forming a bit line over capacitor array of memory cells having such rings is also disclosed.

REFERENCES:
patent: 5118640 (1992-06-01), Fujii et al.
patent: 5126916 (1992-06-01), Tseng
patent: 5155056 (1992-10-01), Jeong-Gyoo
patent: 5229314 (1993-07-01), Okudaira et al.

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