Process for fabricating a high performance PNP and NPN structure

Metal working – Method of mechanical manufacture – Assembling or joining

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29576E, 29576W, 29578, 148 15, 148174, 148175, 148187, 156643, 156653, 156657, 357 20, 357 34, 357 50, 357 56, H01L 21203, H01L 2122

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043786308

ABSTRACT:
Disclosed is the fabrication and structure of very small integrated circuit devices of both PNP and NPN types with very high speeds and low power requirements. The structure provides vertical NPN and lateral PNP transistors formed within the same semiconductor chip. The base width of the lateral PNP transistor is very narrow (approximately 300 to 400 nanometers). This narrow dimension is in part obtained by using a well defined chemically vapor deposited (CVD) oxide mask instead of conventional lithographic masking. To eliminate the emitter current injecting into the substrate the P+ emitter and P+ collector of the PNP transistor are bounded by a silicon nitride and silicon dioxide dielectric layer.

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patent: 4319932 (1982-03-01), Jambotkar
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patent: 4333227 (1982-06-01), Horng et al.
patent: 4338138 (1982-07-01), Cavaliere et al.
Barson, F., "Improved NPN Process & Structure", IBM Tech. Discl. Bull., vol. 23, No. 9, Feb. 1981, pp. 4166-4167.
Berger, H. H., "Method of Producing a Lateral Transistor", Ibid., vol. 23, No. 3, Aug. 1980, pp. 1089-1090.
Wieder, A. W., "Processing for a Lateral PNP Transistor . . . ", Ibid., vol. 21, No. 10, Mar. 1979, pp. 4050-4052.
Yeh, T. H., "Self-Aligned Integrated NPN . . . Structures", Ibid., vol. 22, No. 9, Feb. 1980, pp. 4047-4051.
Feth et al., "Thin Base Lateral PNP Transistor Structure", I.B.M. Tech. Discl. Bull., vol. 22, No. 7, Dec. 1979, pp. 2939-2942.

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