Method for making dynamic random access memory with fin-type sta

Details Method for making dynamic random access memory with fin-type sta Method for making dynamic random access memory with fin-type sta

1991-12-20

1996-11-12

Tsai, H. Jey

Fishing, trapping, and vermin destroying

437 60, 437919, H01L 2170, H01L 2700

Patent

active

055739679

ABSTRACT:
A method is described for fabricating a DRAM having a fin-type stacked capacitor. The method begins by forming a MOSFET source/drain and gate structure on a silicon substrate. The gate electrode is composed of a first polysilicon layer. A first insulator layer composed at least in part of silicon nitride is formed over the device and field oxide areas. The fin-type stacked capacitors are now formed by depositing a second polysilicon layer over the device and field oxide areas. Alternating layers of polysilicon and insulator are deposited over the device and field oxide areas with the first polysilicon layer being in contact to the device areas for electrical contact and the last polysilicon layer being the topmost of the alternating layers. The stack of alternating polysilicon and insulator layers are now patterned to form the basis of the stacked capacitors. The exposed edges of the insulator layers are controlably and laterally isotropic etched to increase the planned surface area of the capacitor by forming fin-type structures. A fourth polysilicon layer is deposited over the device and field oxide areas to complete the lower electrode of the stacked capacitor. A capacitor dielectric layer is formed over the lower electrode of the capacitor and the top polysilicon electrode is deposited thereover to complete the stacked capacitor.

REFERENCES:
patent: 4700457 (1987-10-01), Matsukawa
patent: 4742018 (1988-05-01), Kimura et al.
patent: 5053351 (1991-10-01), Fazan et al.
patent: 5196365 (1993-03-01), Gotou
patent: 5240871 (1993-08-01), Doan et al.
Gura et al, 3-dimensional stacked capacitor all for 16M and 64M DRAMs pp. 592-595, IEDM 1988.

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